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Publications
The papers are posted here only for timely research dissemination; not for redistribution.
Journal Papers
[J26] Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory
D. Chen, J. Edstrom, Y. Gong, P. Gao, L. Yang, M. McCourt, J. Wang, and N. Gong,
to appear in IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 2017.
[J25] Data-Driven Intelligent Efficient Synaptic Storage for Deep Learning
J. Edstrom, Y. Gong, D. Chen, J. Wang, N. Gong,
to appear in IEEE Trans. on Circuits and Systems II, 2017.
[J24] Data-Pattern Enabled Self-Recovery Low-Power Storage System for Big Video Data
J. Edstrom, D. Chen, Y. Gong, J. Wang, N. Gong,
to appear in IEEE Trans. on Big Data, 2017.
[J23] SPIDER: Sizing-Priority Based Application-Driven Memory for Mobile Video Applications
N. Gong, S. A. Pourbakhsh, X. Chen, X. Wang, D. Chen, and J. Wang,
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 2017, 25(9): 2625-2634.
[J22] PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low Power Microprocessors
J. Wang, N. Gong, and Eby G. Friedman,
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 2016, 24(2): 613-624. [pdf]
[J21] cNV SRAM: CMOS Technology Compatible Non-volatile SRAM based Ultra-low Leakage Energy Hybrid Memory System
J. Wang, L. Wang, H. Yin, Z. Wei, Z. Yang, and N. Gong,
IEEE Trans. on Computers, 2016, 65(4): 1055-1067. [pdf]
[J20] A Novel Thermal-aware Structure of TSV Cluster in 3D IC
L. Hou, J. Fu, J. Wang, and N. Gong,
Elsevier's Microelectronic Engineering, 2016, 153(3): 110-116. [pdf]
[J19] TM-RF: Aging Aware Power Efficient Register File Design for Modern Microprocessors
N. Gong, J. Wang, S. Jiang, and R. Sridhar,
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 2015, 23(7): 1196-1209. [pdf]
[J18] Variation Aware Sleep Vector Selection in Dual Vt Dynamic OR Circuits for Low Leakage Register File Design
N. Gong, J. Wang, and R. Sridhar,
IEEE Trans. on Circuits and Systems I, 2014, 61(7): 1970-1983. [pdf]
[J17] Ultra-Low Voltage Split-data-aware Embedded SRAM for Mobile Video Applications
N. Gong, S. Jiang, A. Challapalli, S. Fernandes, and R. Sridhar,
IEEE Trans. on Circuits and Systems II, 2012, 59(12): 883-887. [pdf]
[J16] Clock-biased Local Bit Line for High Performance Register Files
N. Gong, J. Wang, S. Jiang, and R. Sridhar.
Electronics Letters, 2012, 48 (18): 1104-1105. [pdf]
[J15] Hybrid-Cell Register Files Design for Improving NBTI Reliability
N. Gong, S. Jiang, J. Wang, B. Aravamudhan, K. Sekar, and R. Sridhar.
Microelectronics Reliability, 2012, 52 (9): 1865-1869. [pdf]
[J14] Low Power and High Performance Dynamic CMOS XOR/XNOR Gate Design
J. Wang, N. Gong
L. Hou, X. Peng, S. Geng, and W. Wu.
Microelectronic Engineering, 2011, 88(8): 2781-2784. [pdf]
[J13] Leakage Current, Active Power, and Delay Analysis of Dynamic Dual Vt CMOS Circuits under P-V-T Fluctuations
J. Wang, N. Gong, L. Hou, X. Peng, S. Geng, and W. Wu,
Microelectronics Reliability, 2011, 51(9-11): 1498-1502, 2011 [pdf]
[J12] Robustness Aware High Performance High fan-in Domino OR Logic Design
N. Gong, J. Wang, and B. Guo.
Journal of Semiconductors, 2009, 30(6): 889-892.
[J11] Analysis and Optimization of Leakage Current Characteristics in Sub-65nm Dual Vt Footed Domino Circuits
N. Gong, B. Guo, J. Lou, and J. Wang
Microelectronics Journal, 2008, 39(9): 1149-1155. [pdf]
[J10] Performance Estimation for Dual Threshold Domino OR and the Analysis for Its Availability under Process Variation
J. Wang, N. Gong, W. Wu, and L. Dong
Chinese Journal of Electronics, 2010, 38(11): 2611-2615.
[J9] Low Power and High Performance Zipper CMOS Domino Full-adder Design in 45 nm Technology
J. Wang, N. Gong, S. Geng, L. Hou, W. Wu, and L. Dong
Chinese Journal of Electronics, 2009, 37(2): 266-271.
[J8] Monte Carlo Analysis of a Low Power Domino Gate Under Parameter Fluctuation
J. Wang, W. Wu, N. Gong, L. Hou, and D. Gao.
Journal of Semiconductors, 2009, 30 (12): 2364-2371.
[J7] Temperature and Process Variations Aware Dual Vt Footed Domino Circuits Leakage Management
N. Gong, J. Wang, B. Guo, and J. Pang.
Journal of Semiconductors, 2008, 29(12): 2364-2371.
[J6] Charge Self-compensation Technology Research for Low power and High Performance Domino Circuits
J. Wang, N. Gong, L. Hou, W. Wu, and L. Dong.
Journal of Semiconductors, 2008, 29(7): 1412-1416.
[J5] Calculations of Two Dimensional Electron Gas Distributions in AlGaN/GaN Material System
B. Guo, N. Gong, and F. Yu.
Chinese Physics, 2008, 17(1):290-295.
[J4] PN Mixed Pull-down Network Domino XOR Gate Design in 45nm Technology
J. Wang, N. Gong, S. Geng, L. Hou, W. Wu, and L. Dong.
Journal of Semiconductors, 2008, 29(12): 2443-2448.
[J3] A Novel P-type Domino AND Gate Design in Sub-65nm CMOS Technologies
J. Wang, N. Gong, W. Wu, and L. Dong.
Journal of Semiconductors, 2007, 28(11):1818-1823.
[J2] Monte Carlo Simulation of The Hole Transport Properties for Wurtzite GaN
B. Guo, N. Gong, and J. Shi.
Chinese Physics. 2006, 55(5):2470-2475.
[J1] Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies
B. Guo, N. Gong, and J. Wang.
Journal of semiconductors, 2006, 5(5): 804-811.
Conference Papers
[C37] Bringing Offline Mining to Online Learning System: Low-Cost and Efficient Self-Healing Synaptic Storage for Deep Learning
J. Edstrom, D. Chen, Y. Gong, and J. Wang N. Gong,
IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Baltimore, MD, accepted as Late Breaking News.
[C36] Data-Pattern Enabled Self-Recovey Multimedia Storage System for Near-Threshold Computing
N. Gong, J. Edstrom, D. Chen, and J. Wang
IEEE International Conference on Computer Design (ICCD'16), Phoenix, AZ, Oct. 2016, accepted.
[C35] Data-Driven Low-Cost On-Chip Memory with Adaptive Power-Quality Trade-off for Mobile Video Streaming
D. Chen, J. Edstrom, X. Chen, W. Jin, J. Wang, and N. Gong
International Symposium on Low Power Electronics and Design (ISLPED'16), San Francisco, CA, 2016, accepted (Best Paper Nomination).
[C34] Dummy TSV Based Bit-line Optimization in 3D On-chip Memory
X. Chen, S. A. Pourbakhsh, N. Gong, and J. Wang
2016 IEEE International Conference on Electro/Information Technology, Grand Forks, ND, 2016, accepted (Best Paper Award).
[C33] RF-Powered Battery-less Wireless Sensor Network in Structure Monitoring
R. Ge, H. Pan, Z. Lin, N. Gong, and J. Wang
2016 IEEE International Conference on Electro/Information Technology, Grand Forks, ND, 2016, accepted.
[C32] Sizing-Priority Based Low-Power Embedded Memory for Mobile Video Applications
S. A. Pourbakhsh, X. Chen, D. Chen, X. Wang, N. Gong, and J. Wang
International Symposium on Quality Electronic Design (ISQED), 2016, Santa Clara, CA, accepted (Best Paper Nomination).
[C31] Luminance Adaptive Smart Video Storage System
J. Edstrom, D. Chen, J. Wang, H. Gu, E. A. Vazquez, M. McCourt, and N. Gong
IEEE International Symposium on Circuits and Systems (ISCAS), 2016, Montreal, Canada, accepted.
[C30] VCAS: Viewing Context Aware Power-Efficient Mobile Video Embedded Memory
D. Chen, X. Wang, J. Wang, and N. Gong
28th IEEE International SoC Conference (SoCC’15), Beijing, China, pp.333-338.
[C29] Phase Change Material for Thermal Management in 3D Integrated Circuits Packaging
M. Li, N. Gong, J. Wang, and Z. Lin.
48th International Symposium on Microelectronics, 2015, Orlando, USA, pp.216-219.
[C28] A Novel Thermal-Aware Structure of TSV Cluster in 3D IC
L. Hou, J. Fu, J. Wang, and N. Gong
41st International Conference on Micro- and Nanofabrication and Manufacturing (MNE'15), 2015, Orlando, USA, pp.216-219.
[C27] Novel CMOS Technology Compatible Nonvolatile on-chip Hybrid Memory
Z. Yang, L. Hou, J. Wang, and N. Gong
IEEE 11th International Conference on ASIC (ASICON'15), 2015, Chengdu, China.
[C26] Reusable IO Technique for Improved Utility of IC Test Circuit Area
J. Zhang, J. Wang, L. Hou, and N. Gong
IEEE 11th International Conference on ASIC (ASICON'15), 2015, Chengdu, China.
[C25] DCPG: Double-Control Power Gating Technique for a 28 nm Cortex™-A9 MPCore Quad-core Processor
Q. Liang, P. Wan, L. Hou, J. Wang, and N. Gong
IEEE 11th International Conference on ASIC (ASICON'15), 2015, Chengdu, China.
[C24] Viewing Context Adaptive On-chip Video Memory
D. Chen, J. Wang, and N. Gong
48th International Symposium on Microelectronics, 2015, Orlando, USA, pp.216-219.
[C23] Novel Bidirectional IO Multiplexing Circuit Design
J. Zhang, J. Wang, and N. Gong
2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT'14), 2014, Guilin, China. [pdf]
[C22] Analysis And Design Of CMOS Charge Pump for EEPROM
H. Yin, X. Peng, J. Wang, Z. Wei, and N. Gong
2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT'14), 2014, Guilin, China. [pdf]
[C21] Novel Local Bit Line Design Based on Forced-Keeper Technique for On-Chip Memories
Z. Yang, J. Wang, L. Wang, L. Hou, and N. Gong
2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT'14), 2014, Guilin, China. [pdf]
[C20] Novel CMOS SRAM Voltage Latched Sense Amplifier Design Based on 65 nm Technology
Z. Wei, X. Peng, J. Wang, H. Yin, and N. Gong
2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT'14), 2014, Guilin, China. [pdf]
[C19] A Low Power CMOS Technology Compatible Non-volatile SRAM Cell
L. Wang, J. Wang, Z. Yang, L. Hou, and N. Gong
2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT'14), 2014, Guilin, China. [pdf]
[C18] Application-Driven Power Efficient ALU Design Methodology for Modern Microprocessors
N. Gong, J. Wang, and R. Sridhar.
International Symposium on Quality Electronic Design (ISQED’13), 2013, Santa Clara, CA. [pdf]
[C17] Variation-and-Aging Aware Low Power embedded SRAM for Multimedia Applications
N. Gong, S. Jiang, A. Challapalli, M. Panesar, and R. Sridhar.
25th IEEE International SoC Conference (SoCC’12), 2012, Niagara Falls, NY, USA, 21-26. [pdf]
[C16] Novel Adaptive Keeper LBL Technique for Low Power and High Performance Register files
N. Gong, G. Tang, J. Wang, and R. Sridhar.
24th IEEE International SoC Conference (SoCC’11), 2011, Taipei, Taiwan, 30-35. [pdf]
[C15] Low Power Tri-state Register Files Design for Modern Out-of-order Processors
N. Gong, G. Tang, J. Wang, and R. Sridhar.
24th IEEE International SoC Conference (SoCC’11), 2011, Taipei, Taiwan, 323-328. [pdf]
[C14] PVT Variations Aware Optimal Sleep Vector Determination of Dual Vt Domino OR Circuits
N. Gong, J. Wang, and R. Sridhar.
24th IEEE International SoC Conference (SoCC’11), 2011, Taipei, Taiwan, 359-364.[pdf]
[C13] Optimization and Predication of Leakage Current Characteristics in Wide Domino OR Gates under PVT Variation
N. Gong and R. Sridhar.
23rd IEEE International SoC Conference (SoCC‘10), 2010, Las Vegas, USA, 19-24. [pdf]
[C12] Domino Gate with Modified Voltage Keeper
J. Wang, W. Wu, N. Gong, and L. Hou.
11th International Symposium on Quality Electronic Design (ISQED‘10), 2010, San Jose, USA, pp. 443-446. [pdf]
[C11] Fan-in Sensitive Low Power Dynamic Circuits Performance Statistical Characterization
J. Wang, N. Gong, W. Wu, and L. Hou.
23rd IEEE International SoC Conference (SoCC‘10), 2010, Las Vegas, USA, 321-325. [pdf]
[C10] Using Charge Self-compensation Domino Full-adder with Multiple Supply and Dual Threshold Voltage in 45nm
J. Wang, N. Gong, W. Wu, L. Hou, S. Geng, W. Zhang, and X. Peng.
10th International Conference on Ulimate Integration of Silicon (ULIS’09), 2009, Aachen, Germany, 225-228. [pdf]
[C9] Power and Delay Estimation for Dynamic OR Gates with Header and Footer Transistor Based on Wavelet Neural Networks
J. Wang, N. Gong, W. Wu, L. Zuo, L. Hou, X. Peng, and D. Gao.
10th International Conference on Ulimate Integration of Silicon (ULIS’09), 2009, pp.241-244. [pdf]
[C8] Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks
J. Wang, L. Zuo, N. Gong,D. Gao, S. Geng,W. Zhang, L. Hou, X. Peng, and W. Wu.
2009 International Symposium on Neural Networks (ISNN’09), 2009, Wuhan, China, pp.844-851.
[C7] Effectiveness Analysis of Low Power Technique of Dynamic Logic under Temperature and Process Variations
J. Wang, W. Wu, N. Gong, W. Zhang, and L. Hou.
IEEE 8th International Conference on ASIC (ASICON’09), 2009, Changsha, China, pp.1236-1239.
[C6] Wavelet Neural Networks Based Performance Estimation for Power Gating Domino Circuits
J. Wang, W. Wu, N. Gong, L. Zuo, X. Peng, and L. Hou.
IEEE International Conference on Information and Automation (ICIA’09), 2009, Zhuhai, China, pp.435-438.
[C5] Switching and Leakage Power Modeling for Multiple-supply Dynamic Gate with Delay Constraining Based on Wavelet Neural Networks
J. Wang, W. Wu, N. Gong, L. Zuo, L. Hou, S. Geng, W. Zhang, and D. Gao.
2009 International Joint Conference on Neural Networks (IJCNN’09), 2009, Atlanta, USA, pp.3240-3243.
[C4] Low Power and High Performance Zipper Domino Circuits with Charge Recycle Path
J. Wang, N. Gong, S. Geng, L. Hou, W. Wu, and L. Dong.
9th International Conference on Solid-State and Integrated-Circuit Technology(ICISICT’08), Oct 2008, Beijing, China, pp.2172-2175.
[C3] FPGA-Based Integrated Controller for Liquid Crystal Display
J. Wang, J. Zhang, N. Gong, W. Wu, and L. Dong.
ASIA DISPLAY(DISPLAY’07), March 2007, Shanghai, China, pp.343-346.
[C2] Low Power Wide Dominos Design in sub-65nm CMOS Technologies
J. Wang, N. Gong, L. Hou, W. Wu, and L. Dong.
8th International Conference on Solid-State and Integrated-Circuit Technology (ICISICT’06), Oct. 2006, Shanghai, China, pp.1864-1866.
[C1] Leakage Current Characteristics of Footed Dual Vt Dominos in Nanometer CMOS Technologies
B. Guo, N. Gong, and J. Wang.
8th International Conference on Solid-State and Integrated-Circuit Technology (ICISICT’06), Oct. 2006, Shanghai, China, pp.260-262.
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